1. Technical Field
The present disclosure relates to memory refresh operations in general, and in particular to a method and apparatus for performing refresh operations in high-density memories.
2. Description of Related Art
Dynamic random-access memories (DRAMs) are widely employed in a variety of applications. A typical DRAM has multiple blocks of memory cells, and each memory cell includes a capacitor and an access transistor. The capacitor stores a charge related to the value of data stored in a memory cell, and the access transistor selectively couples the capacitor to a bitline for reading from or writing to the memory cell.
Because of various leakage paths, a charge stored within a capacitor of a memory cell will typically dissipate in less than few tens of milliseconds. In order to maintain the integrity of data stored in a memory cell, the memory cell needs to be periodically refreshed by reading the data in the memory cell and rewriting the read (refreshed) data back into the memory cell before a charge stored in a capacitor has had the opportunity to dissipate.
According to the JEDEC standard, a DRAM chip maintains an internal counter that designates the next segment of the DRAM chip to be refreshed, and a memory controller issues an address-less refresh command to the DRAM chip. Two key JEDEC parameters that are closely associated with refresh operations are tREFI and tRFC. Parameter tREFI specifies the interval at which refresh commands must be sent to each DRAM chip, and parameter tRFC specifies the amount of time that each refresh ties-up the DRAM interface.
Most conventional memory controllers simply send refresh operations whenever tREFI (which dictates a refresh timer) expires. This is sufficient for older computer systems where refresh operations have a relatively low overhead (i.e., completes quickly) and do not delay read and/or write operations for very long. However, for newer DRAM chips, such as 4-Gbyte and 16-Gbyte DRAM chips, a refresh operation takes a very long time to complete. The net effect is a measurable increase in effective memory latency when read and/or write operations are frequently needed to be stalled in order to accommodate refresh operations.
In addition, there has been tremendous interest in non-DRAM memories (such as PCM, RRAM, and STT-RAM) that may come to market in the next ten years. Many recent works have assumed a primary advantage of these non-DRAM memories is their non-volatility. While these non-DRAM memories are indeed “non-volatile” at traditional Flash temperatures (i.e., ≦55° C.), several of these non-DRAM memories suffer from accelerated drift effects at temperatures in the range of server main memory (i.e., ≦95° C.). Drift effect causes a change in the memory cell's resistance value. While drift effect may be manageable in the initial single-bit-per-cell PCM implementations that are currently on the market, dense multi-level cell PCM relies on storing and sensing finer resistance granularities, and drift effect will become more of an issue. Dense, multi-bit implementations that are currently envisioned for hybrid and tiered memory systems are likely to require a refresh-like command in order to combat drift effect in high-temperature server environments. The length of such an operation are much longer than those of DRAMs. For example, the write time of a phase-change memory may have a drift-compensating tRFC that are three times longer than the write time specified for current DRAMs. Thus, it is clear that simple refresh scheduling mechanisms cannot adequately handle refresh operations for high-density memories.
Consequently, it would be desirable to provide an improved method and apparatus for performing refresh operations in high-density memories.